The present invention relates generally to integrated circuits and method of manufacturing and more specifically to a method of manufacturing self-aligned junction isolated complementary insulated gate field effect transistors.
The industry is constantly working toward increasing the device density on a wafer or chip. The number of devices that can be placed on a chip is limited by the size of the device and the electrical interaction. These place restraints on the spacing between devices. Further limitation are in the processing steps dealing with photolithography and the ability to form doped regions of the controllable size and impurity concentration. For junction isolated insulated gate field effect transistors, the design must minimize device latch-up resulting from parasitic bipolar devices. It is also desirable to reduce the capacitance of the device as well as the contact and interconnect system. Hot electron and the substrate current injection is another problem which must be faced for insulated gate field effect transistors as well as reducing the resistance of the contacts and junctions.
Although all of these problems have been addressed singly by the prior art, the industry is continuously searching for complete process flows which address as many of these problems as possible. Thus, it is an object of the present invention to address as many of the design restraints as possible while increasing the density of the devices on a chip.
Another object of the present invention is to provide a process flow with a minimum number of masking steps.
Still another object of the present invention is to provide a unique process for forming a reverse image mask.
Yet another object of the present invention is to minimize latch-up.
A further object of the present invention is to provide a process which allows tailoring of the threshold of the devices.
An even further object of the present invention is to inhibit hot electron and substrate current injection.
A still even further object of the present invention is to provide a reduced resistance of junction in contacts.
Another object of the present invention is to lower the overall capacitance of the integrated circuit.
These and other objects of the invention are attained by forming a first mask on a substrate of a first conductivity type and introduction of second conductivity type impurities to form a second conductivity type well. This is followed by a second mask which is the reversed image of the first mask and introduction of a first conductivity type impurities to form a first conductivity type well. The second mask may be formed by other processes. It is preferred that the second mask edges be self-aligned to the first mask. A gate insulative layer and gate materials are formed on the two well areas. This is followed by forming shallow source and drain regions using the gate as a mask in each of the wells. Next, insulative spacers are formed extending laterally from the first and second gates over the source and drain regions and impurities are introduced to form deeper source and drain regions using the gate and the spacers as a mask. This is followed by the forming of the contacts to the respective layers. The gate material is polycrystalline silicon and the impurity introduction steps are carried out by ion implantation. A metal silicide step is performed to reduce the contact resistance by forming metal silicide over the source and drain regions as well as the gate. Insulative inserts are formed between the device regions by etching and filling by deposition to form planar oxide inserts separating the device regions laterally.
A method of forming self-aligned well regions including the inverse image masking step includes forming the first mask followed by introducing impurities to form the first well region. The inverse mask is formed by applying a second mask layer overfilling the openings in the first mask and covering the first mask. The second mask layer is removed sufficiently to expose at least a portion of the first mask layer. The exposed first mask layer and any first mask layer superimposed thereon is selectively removed to iorm the second mask having the reversed image of the first mask. This is followed by introducing the impurities of the opposite conductivity type to form a second well.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.